The invention relates to a method of placing electronic parts in consideration of a delay in layout of a semiconductor integrated circuit.
Hitherto, in a placement process in a layout design of a semiconductor integrated circuit, the placement process has been performed by setting a function for minimizing the total of virtual wire lengths to a target function. As a conventional technique regarding a layout method of the semiconductor integrated circuit, for example, the technique disclosed in JP-A-8-305745 has been known. According to such a conventional technique, an area where gates are placed is divided into a plurality of portions and when an assignment of the gate to each divided area is decided, a function to minimize a wire length between terminals belonging to each gate is used as a target function, an assignment problem of the gates is converted into a regular formula as a linear programming problem, and the optimum assignment of the gates is determined by using an integer programming method.
According to the above conventional technique, a path delay is not always minimized due to a difference of delay characteristics of the gates. The path delay used here denotes a delay which is caused from an initial point flip-flop to a position before a terminal point flip-flop.
It is an object of the invention to provide a method of placing electronic parts so as to set a path delay to a more proper delay in consideration of the problems in the conventional technique.
According to the invention, the above object is accomplished by a method whereby a delay budget per stage of the gate is calculated from a target machine cycle time and the number of logic stages in a path, a wire length limitation of a net of each stage is calculated from the delay budget and delay characteristics of the gate of each stage, and the wire length limitation is used as a target function of placement.